Instruction Scheduling for TriMedia

Instruction scheduling is a crucial phase in a compiler for very long instruction word (VLIW) processors. This paper describes the instruction scheduler of the second generation compiler for the TriMedia VLIW mediaprocessor family as well as related compiler issues to increase the size of a scheduling unit. The paper discusses the guarded decision tree scheduling unit, how guarded decision trees are scheduled, register allocation and its interaction with instruction scheduling, issue slot assignment, and scheduling of jump operations. Furthermore, the paper presents several experiments that quantify various aspects of scheduling.